CompactDiskLayout

Layout Style

The nodes are arranged on a disk such that the disk's radius is minimized. The layout mostly optimizes the dense placement of the nodes, while edges play a minor role. Hence, the compact disk layout is mostly suitable for graphs with small components whose loosely connected nodes should be grouped and packed in a small area.

Concept

The CompactDiskLayout arranges the nodes on a disk from the inside out packing them as dense as possible. During this iterative process it avoids node overlaps and label overlaps (if activated; see nodeLabelPlacement). In particular, to keep the layout compact the CompactDiskLayout may decide to place a single node or multiple nodes in the center of the disk.

Features

Connected Components

By default, the CompactDiskLayout takes the connected components for the placement of the nodes into account. In that case the nodes of the same component are placed sequentially in the iterative placement process ensuring that they form a visual component. Input graph consisting of multiple components. Compact disk layout.

Node Types

If nodeTypes are defined, the CompactDiskLayout takes these into account instead of the connected components. In particular, nodes of the same type are placed closely together forming a visual component. Input graph with node types 'A', 'B' and 'C'. Compact disk layout taking the node types for the placement of the nodes into account.

From Sketch

Use fromSketchMode to take the coordinates of the input diagram into account when arranging the nodes on the disk. Input graph where the nodes are roughly placed on circles. Compact disk layout taking the coordinates of the input diagram into account.

Node Labeling

The CompactDiskLayout allows for integrated node labeling. Node labels are placed automatically without generating overlaps with other labels or graph elements.

Port Placement Constraints

This layout algorithm handles port placement constraints by applying the PortPlacementStage as a postprocessing step.

Layout Stages

This class provides a configurable pipeline that contains various ILayoutStages. Each ILayoutStage can incorporate preprocessing or postprocessing steps into the layout calculation to streamline the input graph and enhance the resulting layout. Additionally, custom ILayoutStages can be added and executed either before or after the predefined ones.

The following default ILayoutStages are included:

• PortPlacementStage: Assigns edges to ports.
• GroupHidingStage: Removes group nodes and their adjacent edges before layout processing, and reinserts them afterward.
• ComponentLayout: Arranges graph components with customizable styles. Note: This stage is disabled by default.
• GenericLabeling: Efficiently places node and edge labels. The property fillEmptyScope is set to false and stopDuration is set to ZERO.
• SelfLoopRouter: Routes self-loops in a graph, allowing for either orthogonal or rounded routing styles. The property routingStyle is set to ROUNDED.
• ParallelEdgeRouter: Routes multiple edges between the same nodes in parallel.

With these layoutStages the layout algorithm is configured well, so they usually don't need to be changed.